Deserializer
US7257169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jan 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4908
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver for deserializing a stream of data bits, including a single clock which is adapted to generate a first plurality of clock phases, and a sample generator which is adapted to sample the stream so as to generate initial data values of each of the bits at times defined by the first plurality of clock phases.The receiver further includes digital circuitry which is adapted to group the initial values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, and assign each of the phase sets a respective grade in response to at least some of the initial values. The circuitry selects a decoding phase set from the phase sets in response to the respective grades, and decodes the stream in response to initial values of the decoding phase set to generate decoded values of the consecutive bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.