Digital clock recovery circuit
US7257183B2 · kind B2 · utility
9Cited by
8References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.