Ternary CAM with software programmable cache policies
US7257673B2 · kind B2 · utility
7Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2006 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jan 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.