Self-verification of configuration memory in programmable logic devices
US7257750B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.