Digital frequency synthesis clocked circuits
US7257756B2 · kind B2 · utility
5Cited by
2References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31716
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the invention may include a reference input port to receive a reference clock, the reference clock being based on a bypass clock, a feedback input port to receive a feedback clock from a clocked circuit, and logic to compare the reference clock and the feedback clock and to generate an output based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.