Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
US7257795B1 · kind B1 · utility
6Cited by
5References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are disclosed to facilitate routing between a first and second component in a programmable logic device to generate a path with an appropriate amount of delay to satisfy short-path timing constraints efficiently and effectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.