Semiconductor device manufacturing method that includes forming a wiring pattern with a mask layer that has a tapered shape
US7259089B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76835
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask layer, formed to project into the inside of the wiring groove pattern, into a tapered shape; forming a contact hole pattern in the second and first mask layer, and removing the tapered shape portions of the third mask layer; and forming wiring grooves in the second insulation film by etching using the third mask layer, and forming contact holes in the insulation film by etching using the second and first mask layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.