System and method to use dynamic feedback of analog to digital converter sample rate to adaptively lock the sample rate to input frequency
US7259547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jun 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S20/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for dynamically lock the sample rate of an analog to digital (ADC) converter to an input frequency. Specifically, a system for measuring power is disclosed. The system includes an ADC converter, a measuring module, an ADC cycle counter, and a calculation block coupled together. The ADC converter samples an analog input line signal. The measuring module measures a predetermined number of line cycles of the analog input line signal. The ADC cycle counter measures an actual sample count of the analog input line signal by the ADC converter over the predetermined number of line cycles. The calculation block determines an error rate between the actual sample count and an ideal sample count that is based on a predetermined over sample rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.