Multi-bit configuration pins
US7259591B1 · kind B1 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Apr 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data input signal in response to a first control signal and a second control signal. The second circuit may be configured to (i) generate the first control signal and the second control signal and (ii) determine whether the first circuit is coupled to (a) a first logic level circuit when in a first state and (b) an impedance circuit and a second logic level circuit when in a second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.