Pseudo true single phase clock latch with feedback mechanism
US7259605B2 · kind B2 · utility
1Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Oct 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pseudo true single phase clock latch (pseudo “TSPC” latch) includes additional circuitry coupled to three previously floating nodes that can lose data depending upon the amount of leakage current associated with these nodes. The additional circuitry, including a positive feedback circuit, improves the performance of a true single phase clock latch circuit at lower frequencies without significant degradation in high frequency operation of the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.