Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection
US7259699B1 · kind B1 · utility
4Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.