System and method for compensating for error in a sigma delta circuit
US7259704B2 · kind B2 · utility
6Cited by
17References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/358
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.