Synchronous global controller for enhanced pipelining
US7260020B2 · kind B2 · utility
7Cited by
6References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jul 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.