Deferred queuing in a buffered switch
US7260104B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5683
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.