Eclipz wiretest for differential clock/oscillator signals
US7260494B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Jul 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31717
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.