Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US7260595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2003 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.