Cache memory usable as scratch pad storage
US7260682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.