Saving power when in or transitioning to a static mode of a processor
US7260731B1 · kind B1 · utility
19Cited by
95References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Nov 22, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.