SEU and SEFI fault tolerant computer
US7260742B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jan 28, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | May 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1497
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.