Iterative decoding process
US7260766B2 · kind B2 · utility
14Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Aug 21, 2007 |
| Priority date | — |
| Expiry date | Sep 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4115
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and a communication device including a turbo decoder to decode a block of encoded data bits that includes information bits and error detection code bits. The turbo decoder is able to produce a decoded block which includes decoded information bits and decoded error detection code bits. The Turbo decoder is able to determine from the decoded error detection code bits and calculated error detection code bits possible error patterns of the error detection code bits and is able to generate from the possible error patterns and/or from the error detection code bits reliability metrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.