Ferroelectric memory and its manufacturing method
US7262065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/694
Abstract
A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.