Manufacturing process of a semiconductor non-volatile memory cell
US7262098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Feb 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.