Semiconductor device having improved power density
US7262476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2004 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Aug 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.0e12 atoms/cm2. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relativ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.