Wafer-level package for integrated circuits
US7262622B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Jun 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.