Compact inductor with stacked via magnetic cores for integrated circuits
US7262680B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An on-chip inductor device for Integrated Circuits utilizes coils on a plurality of metal layers of the IC with electrical connectors between the coils and a magnetic core for the inductor of stacked vias running between the coils. The magnetic core is made from a series of stacked vias which are deposited between each metal layer of the IC having a coil. The magnetic core desirably includes an array of magnetic bars comprising the magnetic core. The via material of the magnetic core may be both magnetic and electrically conductive. The magnetic and electrically conductive via material may also be used for the planar coil electrical connectors or other electrically conductive parts of the IC, or both, thereby lessening fabrication steps. Films of magnetic material may be formed at the ends of the inductor to provide a closed magnetic circuit for the inductor. A high Q factor inductor of small (e.g., transistor) size is thus obtained. The materials and processes which enable the on-chip inductor device are compatible with ordinary IC fabrication methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.