Hardware-based CABAC decoder with parallel binary arithmetic decoding
US7262722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2006 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Jun 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A binary arithmetic decoding apparatus includes first, second and third pairs of look-up tables and first, second and third multiplexers. The first multiplexer selects between the respective outputs of the two look-up tables of the first pair of look-up tables. The second multiplexer selects between the respective outputs of a first look-up table of the second pair of look-up tables and of a first look-up table of the third pair of look-up tables. The third multiplexer selects between the respective outputs of a second look-up table of the second pair of look-up tables and of a second look-up table of the third pair of look-up tables. The three multiplexers are controlled in common.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.