Compact non-volatile memory cell and array system
US7263001B2 · kind B2 · utility
29Cited by
1References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
NVM arrays include rows and columns of NVM cells comprising a floating gate, a programming element, and a logic storage element. During a programming or erase mode, the floating gate of each cell is charged to a predetermined level. At the beginning of a read mode, all storage elements are pre-charged to a high supply voltage level. Following the pre-charge, selected cells are read to determine stored bit values. A charge status of the floating gate of each cell determines whether the storage element is turned on and the pre-charge voltage is pulled down corresponding to a bit value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.