Clock skew compensation for a jitter buffer
US7263109B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Sep 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/6489
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system to minimize the potential of jitter buffer underflow/overflow resulting from a difference in sampling rates of an audio encoder and an audio decoder are disclosed herein. The difference in sampling rates, or clock skew, can be determined from a difference between an actual amount of data stored in a jitter buffer and the desired, or threshold, amount. A subset of packets from a sequence of packets output to the audio decoder can be altered to compensate for the clock skew, whereby the amount of data associated with the subset of packets is decreased when the sampling rate of the encoder is greater than the sampling rate of the decoder, and the amount of data is increased when the sampling rate of the encoder is less than the sampling rate of the decoder. The present invention finds particular advantage in providing audio data via a packet-switched network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.