Speed-up hardware architecture for CCMP encryption protocol
US7263186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/80
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A speed-up hardware architecture used in wireless encryption/decryption operation comprises: a plurality of operation units, that each operation unit is capable of accomplishing a designated operation independently, further comprising: a data receiving device having two inputs that a first input is used for receiving an external data signal and a second input is used for receiving a supporting signal coming from the other operation unit, wherein when an operating mode of the data receiving device is “normal”, the data receiving device will output the first input, and when an operating mode of the data receiving device is “speed-up”, the data receiving device will output the second input; and an operating device coupling to the data receiving device for processing the data from the data receiving device and outputting the processed data thereafter; and a control unit coupling to every operation unit in the architecture for enabling the operation units which are idle to assist the working operation units for data processing, further comprising: a controlling device coupling to the data receiving device of every operation unit in the architecture for issuing a control signal and chang…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.