Microprocessor system
US7263623B1 · kind B1 · utility
2Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Aug 28, 2007 |
| Priority date | — |
| Expiry date | May 10, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor-based system includes multiple peripherals, which can be accessed by the microprocessor over a system bus, with the aid of address decoding logic. Depending on the required functionality of the system at any time, one or more of the peripherals can be disabled. When a peripheral device is disabled, the address decoding logic of the system is modified to ensure that no attempts are made to access that peripheral device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.