Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
US7265045B2 · kind B2 · utility
15Cited by
7References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Aug 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.