Stochastic reset circuit
US7265595B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.