Amplifier circuit with reduced power-off transients and method thereof
US7265614B2 · kind B2 · utility
4Cited by
3References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Sep 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/305
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an amplifier circuit with reduced power-off transients, an amplifier is provided for receiving an input signal and a reference signal to generate an output signal therefrom when it is enabled, and the amplifier is disabled when the supply voltage to the amplifier drops down to a threshold or to a level higher than the reference signal a threshold. The output stage transistor of the amplifier is applied with a body voltage to suppress the body diode parasitic to the output stage transistor to be forward-biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.