Image processor with noise reduction circuit
US7265784B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2003 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Aug 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/68
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital imaging system includes an image sensor, an interface circuit, a frame buffer and an image processor. The image sensor includes a two-dimensional array of pixel elements and outputs digital signals on a pixel bus as pixel data representing an image of a scene. The interface circuit is coupled to receive the pixel data from the pixel bus. The frame buffer is coupled to store pixel data provided by the interface circuit. The image processor operates to process the pixel data stored in the frame buffer to generate image data for displaying the image of the scene. The interface circuit includes a noise reduction circuit operated to perform signal processing on the pixel data received on the pixel bus for noise reduction. Thus, random noise such as readout noise can be eliminated as pixel data are being transferred from the image sensor and stored in the frame buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.