Reducing sneak currents in virtual ground memory arrays
US7266018B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Apr 11, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sneak currents may be reduced between adjacent input/output groups in addressed memory arrays, even in the case when I/O breaks are ineffective, such as during erase verify. By providing a plurality of intervening, appropriately biased, non-addressed memory cells, a high resistance to sneak currents may be presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.