System and method for hardware accelerated packet multicast in a virtual routing system
US7266120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2002 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Oct 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/6489
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet-forwarding engine (PFE) of a multiprocessor system uses an array of flow classification block (FCB) indices to multicast a packet. Packets are received and buffered in external memory. In one embodiment, when a multicast packet is identified, a bit is set in a packet descriptor and an FCB index is generated and sent with a null-packet to the egress processors which generate multiple descriptors with different indices for each instance of multicasting. All the descriptors may point to the same buffer in the external memory, which stores the multicast packet. A DMA engine reads from the same buffer multiple times and egress processors may access an appropriate transform control block (TCB) index so that the proper headers may be installed on the outgoing packet. The buffer may be released after the last time the packet is read by setting a particular bit of the FCB index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.