Method and apparatus for calculating cyclic redundancy checks for variable length packets
US7266760B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Mar 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Cyclic redundancy checking operations may be performed on a message made up of full words and a partial word. An accumulator value for the cyclic redundancy checking operations may be updated as the full words and partial word are processed. The partial word may be padded with pad bits. The effects of the partial word padding can be removed by performing polynomial division on the accumulator. Polynomial division may be performed using an arrangement where each polynomial division involves half as many bits as its predecessor. Iterative division schemes in which a fixed number of bits are processed in multiple passes may also be used. Hybrid arrangements involving cascaded divisions of different orders and iterative fixed-size division can be used. Unpadded partial words may also be processed using cascaded, iterative, and hybrid schemes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.