Method and apparatus of optimizing the IO collar of a peripheral image
US7266789B2 · kind B2 · utility
5Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2005 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated, or a combination of rotated and non-rotated IO cells may form the IO collar. For each edge of the IC chip having rotated IO cells, each edge may have the same number of stacks of IO cells or a different number of stacks of IO cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.