Method and system for logic equivalence checking
US7266790B2 · kind B2 · utility
6Cited by
6References
44Claims
0Family size
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Key dates
| Filing date | Sep 4, 2003 |
| Grant date | Sep 4, 2007 |
| Priority date | — |
| Expiry date | Oct 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.