Semiconductor on glass insulator with deposited barrier layer
US7268051B2 · kind B2 · utility
10Cited by
12References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus provide for: a silicon on insulator structure, comprising: a glass substrate; a layer of semiconductor material; and a deposited barrier layer of between about 60 nm to about 600 nm disposed between the glass substrate and the semiconductor material, where the glass substrate and semiconductor material are bonded together via electrolysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.