DPRIO for embedded hard IP
US7268582B1 · kind B1 · utility
6Cited by
6References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 22, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.