Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal
US7268600B2 · kind B2 · utility
0Cited by
13References
30Claims
0Family size
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Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector (216) and a glitch detector (208) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.