Technique for operating a delay circuit
US7268605B2 · kind B2 · utility
31Cited by
12References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmissions of the signal through the plurality of data paths. The delay circuit may additionally generate a plurality of signals based on the staggered transmissions. Each of the plurality of data paths in the delay circuit may comprise at least one of an inverter, a logic gate, a flip-flop, a latch, a register, or a resistor-capacitor (RC) delay element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.