Systems and methods for programming floating-gate transistors
US7269046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2006 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | May 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.