Semiconductor memory device and semiconductor device group
US7269053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.