Non volatile semiconductor memory device having a multi-bit cell array
US7269085B2 · kind B2 · utility
19Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Mar 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.