Arrangement for dynamic DC offset compensation
US7269234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jul 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital arrangement for selecting a channel coefficient and DC estimate comprises a demultiplexer receiving a digital input signal splitting the digital input signal into a first and second signal, a first joint detection unit receiving the first signal generating a first channel coefficient and DC estimate, a second joint detection unit receiving the second signal generating a second channel coefficient and DC estimate, a first and second error determination unit receiving the first and second channel coefficients and DC estimates, respectively for generating a first and second error signal, a decision unit receiving the first and second error signals generating a control signal, and a selection unit controlled by the control signal for selecting the first or second channel coefficient and DC estimate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.