Aggregated run-to-run process control for wafer yield optimization
US7269526B2 · kind B2 · utility
4Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | May 4, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | May 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67276
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing wafers in a batch processing tool that optimizes yield by minimizing within batch wafer variation in a wafer process. In a tool having a plurality of available wafer positions for a batch process, the method is useful when less than a full batch of wafers is to be processed. All of the possible wafer position combinations are determined and the within batch variation for each position combination is determined. The wafer position combination resulting in the least amount of within batch variation in the wafer process is then selected as the wafer placement combination for use in the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.