Method using receive and transmit protocol aware logic modules for confirming checksum values stored in network packet
US7269661B2 · kind B2 · utility
15Cited by
9References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Jan 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/325
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network processor with modified transmit and receive paths in order to achieve higher bandwidth between a network interface to an attached user's circuit. The network processor includes a shared data buffer in which the network interface, processor, and user's interface all have access. The network processor also includes protocol aware logic that offloads much of the processor's tasks, and improves bandwidth. This abstract is provided as a tool for those searching for patents, and not as a limitation on the scope of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.