Method and apparatus for reducing system inactivity during time data float delay and external memory write
US7269704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2005 |
| Grant date | Sep 11, 2007 |
| Priority date | — |
| Expiry date | Oct 17, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises the following. An external bus circuit is coupled to the internal and external data busses. The bus interface circuit is configured to receive read and write signals for data request data. In response, the bus interfaces circuit transmits a wait signal until data from the external peripheral is available on the internal data bus. The wait signal indicates that the external and internal data busses are not available for other purposes. After the processor has received or transmits the data, the bus interface circuit stops transmitting the wait signal and transmits a busy signal. The busy signal indicates that the internal data bus is available and the external data bus is not available for other purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.